Verification Engineer

Start Date: September 2024

Contract Length: 6 Months

Location / Remote Working: Hybrid, Manchester; 2 Days in office

Pay Rate: £390 - £420 per day - Inside IR35

Our client is a well-known semiconductor manufacturer who is looking for a Verification Engineer to join their hardware team. They are looking for someone who has solid experience with RTL, Jasper and SystemVerilog.

Responsibilities:

• Identifying and developing new hardware simulations
• Formal property verification
• Architect and implement verification environments
• Improve on existing testbenches
• Writing assertations using SVA with Cadence

Essential Skill Set:

• Experience in working with constrained-random RTL verification including ownership of a suitably complex verification environment and creating testbenches
• Experience developing re-usable and scalable code whilst having in-depth knowledge of SV-UVM
• Solid software engineering skills including understanding of object-oriented programming, data structures, and algorithms
• Familiar with the tools and processes for developing testbenches and finishing all aspects of the verification process (Questasim/VCS/Verdi/Xcelium simulators, SystemVerilog and UVM)

Desirable Skill Set:

• Multiprocessing microarchitecture
• AMBA5 CHI, AMBA4 ACE or AXI